The present invention relates to a field-effect semiconductor device capable of operating at a low voltage and also to a method of fabricating it.
FIG. 2 shows a final cross-sectional view of a semiconductor device fabricated by the prior art fabrication method. A semiconductor substrate surface 102 has N-type semiconductor regions over which a gate-insulating film 103 is formed by thermal oxidation processing. A channel implant 104 is made into the N-type semiconductor regions through the gate-insulating film. A thin film of silicon 105 is deposited on the gate-insulating film by a CVD method. Boron ions are implanted as P-type impurities, and then the laminate is heat-treated to make the thin silicon film P-type. Thereafter, a silicide film 106 is deposited on the polysilicon thin film. Photoresist is patterned. The silicon thin film and the silicide film are etched at the same timing, thus forming gate electrodes. Then, the surface of the semiconductor substrate is thermally oxidized to form an oxide film. Subsequently, impurity ions are implanted, using the gate electrodes as a mask. In this way, source/drain regions 108 are formed. This is followed by formation of an interlayer film 109 of BPSG over the whole surface. For example, this interlayer film is formed by CVD or other method, followed by a heat treatment for planarizing the surface. Then, the interlayer film is selectively etched and heat-treated. Contact holes communicating with the source/drain regions and with the gate electrodes are formed. Then, a metallic material or the like is formed as a film over the whole surface by vacuum evaporation, sputtering, or other method. Thereafter, photolithography and etching steps are carried out. In this manner, a metal interconnect pattern 110 is formed. Finally, the whole substrate is protected with a surface-protecting film.
Portable appliances and desktop appliances normally use electric batteries as their power supplies. In order to achieve miniaturization of the appliances and lower electric power consumption, appliances which are required to be operated at a power voltage (about 1.5 V) supplied from a single dry battery are increasingly produced. Accordingly, low-voltage operation ICs are cited as important items to be developed.
In order to lower the operating voltage, it is necessary to suppress the threshold voltage of the MOS transistor. However, where the threshold voltage of the MOS transistor is decreased down to a value (e.g., about 0.5 V) which is necessary for 1.5 V-operation, there arises the problem that the leakage current from the MOS transistor increases. If the leakage current increases, the electric battery is consumed quickly even if the battery-driven portable appliance is not used. As a result, the battery runs down prematurely.
With the above-described semiconductor fabrication method, however, before the implantation of ions into the source/drain regions, the oxide film is formed by thermal oxidation and so the process temperature is high. P-type boron in the polvsilicon diffuses into the silicide film, thus reducing the concentration in the polysilicon. In the field-effect transistor having the gate electrode of this construction, a depletion layer is formed within the gate electrode. Therefore, the threshold voltage varies, the channel conductance decreases, and the leakage current increases.
In order to solve the foregoing problems, the following fabrication means are taken.
(1) A gate-insulating film is formed on a surface of a semiconductor substrate. A gate electrode is formed on the gate-insulating film to make a pattern. A CVD-grown dielectric film having a thickness of 5 to 1000 xc3x85 is formed at a temperature lower than 850xc2x0 C. over the whole surface of the semiconductor substrate. Impurity ions are implanted into the surface of the semiconductor substrate, using the gate electrode as a mask. Thus, source/drain regions are formed.
(2) The aforementioned gate electrode is formed in the manner described now. A thin film of silicon is formed on the gate-insulating film. P-type impurity ions are implanted into the thin film of silicon. The semiconductor substrate is heat-treated at a temperature of 700-900xc2x0 C. to make the silicon film P-type. A silicide film is formed on the silicon film.
(3) The source/drain regions are heat-treated at a temperature of 800 to 1050xc2x0 C. for a short time of less than 3 minutes to activate them.
(4) A method of fabricating a semiconductor device having N-type semiconductor regions and P-type semiconductor regions formed on a surface of a semiconductor substrate, P-type insulated-gate field-effect transistors and N-type insulated-gate field-effect transistors installed in the N- and P-type semiconductor regions, respectively, at a high integration density, said method comprising the steps of:
forming a gate-insulating film on the surface of said semiconductor substrate;
forming a thin film of silicon on said gate-insulating film;
implanting P-type impurity ions into the thin film of silicon overlying said N-type semiconductor regions;
implanting N-type impurity ions into the thin film of silicon overlying said P-type semiconductor regions;
heat-treating said semiconductor substrate at a temperature of 700-900xc2x0 C. to make said thin films of silicon P-type and N-type, respectively;
forming a silicide film on said thin films of silicon;
selectively etching said thin films of silicon and said silicide film at the same time to form gate electrodes on said gate-insulating film;
forming a CVD-grown dielectric film having a thickness of 5 to 1000 xc3x85 over the whole surface of the semiconductor substrate;
implanting P-type impurity ions into surfaces of said N-type semiconductor regions while using said gate electrodes as a mask, thus forming source/drain regions; and
implanting N-type impurity phosphorus ions into surfaces of said P-type semiconductor regions while using said gate electrodes as a mask, thus forming source/drain regions.
(5) The steps of forming said source/drain regions are carried out by activation which is performed by a heat treatment that is conducted at a temperature of 800-1050xc2x0 C. within a short time of less than 3 minutes.
(6) One comprising:
a gate-insulating film formed on a semiconductor substrate;
gate electrodes consisting of P- and N-type polysilicon thin films and plural thin conductive films formed over said gate-insulating film;
source and drain regions which are formed over a surface of said semiconductor regions on opposite sides of said gate electrodes and spaced from each other; and
said P- and N-type polysilicon thin films being doped with impurities at an impurity concentration sufficient to prevent depletion layers from being formed in said P- and N-type polysilicon thin films when a voltage is applied between each of the conductive thin films and said semiconductor substrate.
(7) Said P-type polysilicon thin film is doped with a P-type impurity at a concentration in excess of 2E19 atoms/cm3. Said N-type polysilicon thin film is doped with an N-type impurity at a concentration in excess of 2E19 atoms/cm3.
(8) A method of fabricating a CMOS semiconductor device having N-type and P-type semiconductor regions formed on a surface of the semiconductor substrate and N-type and P-type gate-insulated field-effect transistors installed in the P- and N-type semiconductor regions, respectively, at a high integration density, said method comprising the steps of:
forming a gate-insulating film on the surface of said semiconductor substrate;
implanting N-type impurity ions into the surfaces of said N-type semiconductor regions to form channel doped regions;
implanting P-type impurity ions into the surfaces of said P-type semiconductor regions to form channel doped regions;
forming a thin film of silicon on said gate-insulating film;
implanting P-type impurity ions into the thin film of silicon overlying said N-type semiconductor regions;
implanting N-type impurity ions into the thin film of silicon overlying said P-type semiconductor regions;
heat-treating said semiconductor substrate at a temperature of 700-900xc2x0 C. to make said silicon thin films P-type and N-type, respectively;
forming a silicide film on said silicon films;
selectively etching said silicon films and said silicide film at the same time to form gate electrodes over the gate-insulating film;
forming a CVD-grown dielectric film having a thickness of 5 to 1000 xc3x85 over the whole surface of said semiconductor substrate;
implanting P-type impurity ions into the surfaces of said N-type semiconductor regions, using said gate electrodes as a mask, to form source/drain regions;
implanting N-type impurity phosphorus ions into the surfaces of said P-type semiconductor regions, using said gate electrodes as a mask, to form source/drain regions; and
heat-treating said source/drain regions at a temperature of 800 to 1050xc2x0 C. for a short time of less than 3 minutes so as to activate the source/drain regions, whereby completing them.
(9) During said step of forming said channel doped regions, phosphorus or arsenic ions are implanted as the N-type impurity ions at an acceleration energy of less than 30 KeV or less than 70 KeV, respectively. BF2 is implanted as the P-type impurity ions at an acceleration energy of less than 70 KeV.
(10) During said step of forming said channel doped regions, BF2 ions are implanted as the P-type impurity ions into the whole surface of the semiconductor substrate and then phosphorus ions are implanted as the N-type impurity ions into the surfaces of said N-type semiconductor regions, thus forming the channel doped regions.
(11) A method of fabricating said CMOS semiconductor device, comprising the steps of:
forming a thin film of silicon on said gate-insulating film;
implanting P-type impurity ions into said thin film of silicon;
heat-treating said semiconductor substrate at a temperature of 700-900xc2x0 C. to make said thin film of silicon P-type;
forming a silicide film on said thin film of silicon;
selectively etching said thin film of silicon and said silicide film at the same time to form gate electrodes on the gate-insulating film;
heat-treating the whole surface of said semiconductor substrate at a temperature of 800-1050xc2x0 C. in an oxygen ambient for a short time of less than 3 minutes to form a dielectric film over the whole surface;
implanting N-type impurity ions into surfaces of said P-type semiconductor regions, using said gate electrodes as a mask, to form source/drain region and, at the same time, implanting ions into said silicide film;
implanting P-type impurity ions into surfaces of said N-type semiconductor regions, using said gate electrodes as a mask, to form source/drain regions; and
heat-treating said source/drain regions at a temperature of 800-1050xc2x0 C. for a short time of less than 3 minutes to activate the source/drain regions and, at the same time, diffusing an N-type impurity from said ion-implanted silicide film into said thin films of silicon under the silicide film to change said P-type thin films of silicon on the surfaces of said semiconductor regions into N-type thin films of silicon.
(12) A semiconductor device having said P- and N-type gate-insulated field-effect transistors installed at a high integration density in said N- and P-type semiconductor regions, respectively, formed on the surface of the semiconductor substrate. A gate-insulating film of 30 to 200 xc3x85 is formed on the surface of the semiconductor substrate. The gate electrodes formed on said gate-insulating film has a minimum length of 1.0 xcexcm.
(13) A method of fabricating a semiconductor, comprising the steps of:
forming a P-type well layer in a semiconductor substrate, using a mask; and
then forming an N-type well layer in the semiconductor substrate.
(14) A method comprising the steps of:
forming a silicon oxide film and a silicon nitrite film on a semiconductor substrate successively;
selectively removing said silicon nitrite film by photomask processing to define regions of said P well layer;
implanting P-type impurity ions into said semiconductor substrate;
forming a silicon oxide film in the P well regions from which said silicon nitrite film has been removed;
removing said silicon nitrite film to define regions of said N well layer;
implanting N-type impurity ions into said semiconductor substrate; and
heat-treating said semiconductor substrate to diffuse and activate the impurities.